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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The open ISA philosophy and the standardization efforts of RISC-V International
- RISC-V conceptual model: Load-Store architecture, register file organization, and byte ordering
- Comparative analysis with ARM, x86, and POWER architectures: evaluating trade-offs for heterogeneous computing
- Ecosystem maturity review: Key players like SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Standardized interfaces: RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Unprivileged Architecture specification: CSR mapping, exception handling mechanisms, and memory hierarchies
- RV32I and RV64I instruction sets with ABI compliance for cross-platform binary portability
- Memory ordering conventions and barrier instructions essential for multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Bitness-aware programming strategies tailored for 32-bit and 64-bit RISC-V targets
- Calling conventions and stack frame management for embedded and real-time software systems
Compiler Toolchain Proficiency
- LLVM-based toolchain components: Clang, LLVM, and Binutils for RISC-V cross-compilation
- Linker scripts, section management, and memory layout configuration for bare-metal and RTOS environments
- Leveraging compiler intrinsics, optimizing code levels, and profiling-driven performance tuning
- Open-source toolchain development workflows: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Rust systems programming for RISC-V: utilizing zero-cost abstractions, managing unsafe memory, and bare-metal development
- No-Std environments: implementing custom linkers, device drivers, and memory-mapped I/O
- Developing BSPs for Zephyr RTOS and Buildroot on RISC-V targets
- Peripheral interfacing techniques: GPIO, I2C, SPI, UART, and DMA controller programming
Power and Performance Optimization
- Clock gating, power domain management, and optimization of low-power modes
- Cycle-accurate performance analysis using simulation profilers and hardware performance counters
- Tuning real-time interrupt latency for safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- OpenSBI (SBI specification implementation): developing bootloader firmware
- Implementing UEFI/EDK II on RISC-V for modern firmware boot stack development
- Porting Coreboot and U-Boot to RISC-V single-board computers
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel: device tree overlays, CPU topology, and interrupt controller (AIA) driver development
- Developing Vendor BSPs and configuring kernels for custom SoC platforms
- Enabling file system support, networking stacks, and containerization capabilities (Docker, Kubernetes) on RISC-V hosts
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Network-on-Chip (NoC) design methodologies for RISC-V multi-core processors
- Axi4/CHI cache coherence and inter-processor communication protocols
- Integrating open-source IP: OpenCores, ChIPS Framework, and vendor RTL components
- Designing bus matrices and integrating memory controllers (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- Synthesis and implementation of RISC-V cores on FPGA (e.g., BOOM, VexRiscv, PULP)
- Employing SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
- Using formal verification tools and property-based testing for RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Vector load/store operations, vector-fused multiply-add (VFMA), and matrix computation acceleration
- Variable-length vector operations (VL, VLEN) enabling workload-optimized SIMD execution
- Vector mask operations, segment control, and data type flexibility for DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators via custom extensions and CBAR-based operand interfaces
- Modifying compiler frontends for custom instruction generation and code emission
- Developing hardware-software partitioning strategies for integrating accelerators into production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Neural Processing Unit architecture: systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Applying model quantization techniques (INT8, INT4, FP8) for edge deployment on RISC-V
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-designing the RISC-V host CPU with an AI accelerator NPU for real-time inference pipelines
- Optimizing the memory subsystem: managing HBM/DDR bandwidth for ML model weights and activations
- Managing thermal and power budgets for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Establishing Secure Enclave/TEE architectures for RISC-V: integrating OP-TEE and SEV-class trusted execution environments
- Securing the boot chain: establishing a root of trust, implementing secure boot, and performing measured launch attestation
Cryptographic Acceleration
- Leveraging RISC-V cryptographic extensions (Zk, Zkr, K) for SHA, AES, RSA, RSA-PSS, and ECC acceleration
- Integrating Post-quantum cryptography (PQC) for next-generation RISC-V processors
- Implementing side-channel attack mitigation techniques: constant-time programming, masking, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- ISA extension design methodology: encoding, creating encoding tables, analyzing ABI impacts, and submitting to RISC-V International specifications
- Designing custom register files with CBAR (Custom Base Address Registers) for operand dispatch
- Implementing instruction pipelining, hazard detection, and pipeline modifications for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions: generating directed versus constraint-random stimuli
- Establishing regression testing frameworks and coverage-driven verification for architectural modifications
- Conducting interoperability testing to ensure custom instructions operate within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for RISC-V automotive processors
- Determining ASIL-Q classification and developing safety manuals for RISC-V silicon IP
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
- Developing Industrial IoT gateways with RISC-V: managing connectivity, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: designing ISA extensions and core configurations for a defined use case
- RTL implementation in SystemVerilog utilizing UVM testbenches and formal verification coverage
- FPGA prototyping, boot firmware development, and bare-metal driver stack integration
- Customizing Linux BSP and toolchains for the custom RISC-V core
- Deploying AI workloads: integrating NPUs, quantizing models, and conducting performance benchmarking
- Validating security: enforcing PMP, implementing secure boot, and benchmarking cryptographic acceleration
- Producing technical architecture documentation, analyzing IP strategies, and presenting to cross-functional teams
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
