Thank you for sending your enquiry! One of our team members will contact you shortly.
Thank you for sending your booking! One of our team members will contact you shortly.
Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The philosophy of open ISAs and the RISC-V International standardization context
- Understanding RISC-V: Load-Store architecture, register files, and byte ordering conventions
- Comparative analysis with ARM, x86, and POWER: evaluating trade-offs for heterogeneous computing systems
- Assessing ecosystem maturity: SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Standardized interfaces: RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Unprivileged Architecture specifications: CSR maps, exception handling mechanisms, and memory hierarchies
- RV32I and RV64I instruction sets, along with ABI compliance for cross-platform binary portability
- Memory ordering conventions and barrier instructions tailored for multiprocessor environments
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Bitness-aware programming techniques for both 32-bit and 64-bit RISC-V targets
- Calling conventions and stack frame management strategies for embedded and real-time software systems
Compiler Toolchain Proficiency
- Navigating the LLVM-based compiler toolchain: Clang, LLVM, and Binutils for RISC-V cross-compilation
- Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments
- Leveraging compiler intrinsics, optimization levels, and profiling-driven code tuning
- Workflows for open-source toolchain development: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Systems programming in Rust for RISC-V: managing zero-cost abstractions, unsafe memory access, and bare-metal development
- Navigating no-Std environments: crafting custom linkers, developing device drivers, and handling memory-mapped I/O
- Developing Zephyr RTOS and Buildroot BSPs for RISC-V targets
- Peripheral interfacing: programming GPIO, I2C, SPI, UART, and DMA controllers
Power and Performance Optimization
- Optimizing clock gating, power domain management, and low-power modes
- Analyzing cycle-accurate performance using simulation profilers and hardware performance counters
- Tuning real-time interrupt latency for safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- OpenSBI (implementing the SBI specification): developing bootloader firmware
- Implementing UEFI/EDK II on RISC-V: building modern firmware boot stacks
- Porting Coreboot and U-Boot to RISC-V single-board computers
Linux Kernel Integration
- Contributing to the mainline RISC-V kernel: managing device tree overlays, CPU topology, and AIA interrupt controller drivers
- Developing Vendor BSPs and configuring kernels for custom SoC platforms
- Enabling file system support, networking stacks, and containerization capabilities (Docker, Kubernetes) on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Design methodologies for Network-on-Chip (NoC) in RISC-V multi-core processors
- Managing Axi4/CHI cache coherence and inter-processor communication protocols
- Integrating open-source IP: utilizing OpenCores, ChIPS Framework, and vendor RTL components
- Designing bus matrices and integrating memory controllers (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores on FPGA platforms (e.g., BOOM, VexRiscv, PULP)
- Applying SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
- Using formal verification tools and property-based testing for core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Accelerating vector load/store, vector-fused multiply-add (VFMA), and matrix computations
- Utilizing variable-length vector operations (VL, VLEN) for workload-optimized SIMD execution
- Leveraging vector mask operations, segment control, and data type flexibility for DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators via custom extensions and CBAR-based operand interfaces
- Modifying compiler frontends to generate and emit code for custom instructions
- Strategies for hardware-software partitioning when integrating accelerators into production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units: employing systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Applying model quantization techniques (INT8, INT4, FP8) for edge deployment on RISC-V
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs alongside AI accelerator NPUs for real-time inference pipelines
- Optimizing memory subsystems: managing HBM/DDR bandwidth for ML model weights and activations
- Budgeting thermal constraints and power limits for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Establishing Secure Enclave/TEE architectures for RISC-V: integrating OP-TEE and SEV-class trusted execution environments
- Securing the boot chain: establishing root of trust, secure boot procedures, and measured launch attestation
Cryptographic Acceleration
- Leveraging RISC-V cryptographic extensions (Zk, Zkr, K extensions) for SHA, AES, RSA, RSA-PSS, and ECC acceleration
- Integrating post-quantum cryptography (PQC) for next-generation RISC-V processors
- Mitigating side-channel attacks through constant-time programming, masking techniques, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Methodologies for ISA extension design: encoding, creating encoding tables, analyzing ABI impacts, and submitting to RISC-V International
- Designing custom register files with CBAR (Custom Base Address Registers) for operand dispatch
- Managing instruction pipelining, hazard detection, and implementing pipeline modifications for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions: generating directed vs. constraint-random stimulus
- Establishing regression testing frameworks and coverage-driven verification for architectural changes
- Conducting interoperability testing to ensure custom instructions adhere to established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for RISC-V automotive processors
- Determining ASIL-Q classification and developing safety manuals for RISC-V silicon IP
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical systems
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
- Developing Industrial IoT gateways with RISC-V: addressing connectivity, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: designing ISA extensions and core configurations for a specific use case
- RTL implementation in SystemVerilog, incorporating UVM testbenches and formal verification coverage
- FPGA prototyping, boot firmware development, and integrating the bare-metal driver stack
- Customizing Linux BSPs and toolchains for the custom RISC-V core
- Deploying AI workloads: integrating NPUs, performing model quantization, and benchmarking performance
- Validating security: enforcing PMP, implementing secure boot, and benchmarking cryptographic acceleration
- Preparing technical architecture documentation, conducting IP strategy analysis, and presenting to cross-functional teams
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
